The present invention relates to a semiconductor device in which a variety of chip IPs are installed on a semiconductor circuit board that is provided with a wiring layer, an evaluation method thereof, and a function setting method thereof.
Recently, the concept of a system LSI with a plurality of LSIs formed on a common substrate has been introduced, and a variety of proposals for design methods for a system LSI have been made. The particular advantages of a system LSI are that memory, for example DRAM, logic LSIs, and analog circuits, such as high-frequency circuits, are stored within a single semiconductor device, and that it is possible to attain an extremely high integration of semiconductor devices of multiple types and multiple functions.
The above-described conventional system LSIs encounter the following problems when the devices are actually formed.
A first problem is that it is difficult to reduce the production cost of the devices. The reason for this is that the cost of development for system LSIs significantly increases, and production yield does not particularly improve.
A second problem is that wiring delays significantly increase. In general, when shrink rules are followed, the height of the device is also lowered, but when that happens, wiring delays depending on RC (R is resistance, C is parasitic capacitance) increase as the cross section of the wires becomes smaller. That is, as far as wiring delays are concerned, miniaturization causes more disadvantages than advantages. One approach to remedy this is to provide a buffer within the wires, however, providing a buffer invites other disadvantages, such as the increase in the area occupied by the device and its power consumption.
A third problem is that it is difficult to reduce noise. Lowering the power source voltage increases the electric current, but it is difficult to inhibit the increase in noise that accompanies this increase in electric current. This is because the SN ratio worsens in proportion to a third power to sixth power of the shrinking ratio, and thus an increase in noise due to miniaturization cannot be avoided. That is, how power source impedance is inhibited is a key factor.
Here, as one approach for securing a large cross section of wiring while achieving a semiconductor device incorporating devices of multiple types and multiple functions, it was thought that semiconductor devices would be achieved that are suitable for low-variety mass-production by the implementation of a chip IP, in which a variety of elements are integrated, onto a semiconductor circuit board, for example a silicon circuit board, having a wiring layer. However, the LSIs within a conventional chip IP are designed as hardware for the IP (hard IP), and the function of this hard IP is unique and fixed like a black box, and thus the structure itself does not meet demands for adaptability to various applications or for a reduction in variety. That is, using conventional methods for building a system LSI, it is difficult to attain semiconductor devices suitable for low variety mass-production.